A wide-range programmable frequency synthesizer based on a finite state machine filter

In this article, an FPGA-based design and implementation of a fully digital wide-range programmable frequency synthesizer based on a finite state machine filter is presented. The advantages of the proposed architecture are that, it simultaneously generates a high frequency signal from a low frequency reference signal (i.e. synthesising), and synchronising the two signals (signals have the same phase, or a constant difference) without jitter accumulation issue. The architecture is portable and can be easily implemented for various platforms, such as FPGAs and integrated circuits. The frequency synthesizer circuit can be used as a part of SERDES devices in intra/inter chip communication in system-on-chip (SoC). The proposed circuit is designed using Verilog language and synthesized for the Altera DE2-70 development board, with the Cyclone II (EP2C35F672C6) device on board. Simulation and experimental results are included; they prove the synthesizing and tracking features of the proposed architecture. The generated clock signal frequency of a range from 19.8 MHz to 440 MHz is synchronized to the input reference clock with a frequency step of 0.12 MHz.

In serial data communication systems, the transmitter and the receiver must be synchronised to reliably access the transmitted data. The transmitter starts normally with converting the data from parallel to serial by multiplexing multi low-frequency parallel data streams into a single higher frequency data stream. An internal frequency generation circuit is required to generate multiple clock frequencies and clock the multiplexers. The high-frequency serialized data is then transmitted through the channel to the receiver. On the other hand, the receiver uses a clock and data recovery circuit (CDR) to extract the clock signal from the received data and demultiplexes the data by the recovered clock, to become a low-frequency parallel data again (Assaad and Alser 20111. Assaad, M and Alser, M. 2011. An FPGA-based Design and Implementation of an All-digital Serializer for Inter Module Communication in SoC. IEICE Electronics Express, 8: 2017–2023.

View all references).

Typically, phase-locked loops (PLLs) and delay-locked loops (DLLs) are widely utilised in the implementation of the frequency synthesiser, clock synchronisation, and clock and data recovery circuits (Maillard, Devisch, and Kuijk 200211. Maillard, X, Devisch, F and Kuijk, M. 2002. A 900-Mb/s CMOS Data Recovery DLL Using Half-frequency Clock. IEEE Journal of Solid-State Circuits, 37: 711–715.

View all references; Mesgarzadeh and Alvandpour 200912. Mesgarzadeh, B and Alvandpour, A. 2009. A Low-power Digital DLL-based Clock Generator in Open-loop Mode. IEEE Journal of Solid-state Circuits, 44: 1907–1913.

View all references; Choi et al. 20114. Choi, J, Kim, ST, Kim, W, Kim, K-W, Lim, K and Laskar, J. 2011. A Low Power and Wide Range Programmable Clock Generator with a High Multiplication Factor. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 19: 701–705.

View all references). Conventional implementations of such PLLs/DLLs are analogue; however, the rapid advances in integrated circuit technology cause their analogue implementations to operate in a very noisy environment (Chung and Lee 20035. Chung, C-C and Lee, C-Y. 2003. An All-digital Phase-locked Loop for High-speed Clock Generation. IEEE Journal of Solid-state Circuits, 38: 347–351.

View all references). Furthermore, considering the progress in improving the overall system performance, stability, and programmability, fully-digital implementations of PLLs/DLLs have become more attractive in many applications than their analogue counterparts. Fully-digital implementations of PLLs/DLLs offer the possibility to achieve low voltage operation, low power consumption, and less sensitivity to noise (since there is no analogue control). Unfortunately, given an identical noise environment and circuit components, PLL has higher jitter than DLL due to phase noise accumulation process (Helal, Straayer, Wei, and Perrott 20088. Helal, BM, Straayer, MZ, Wei, G-Y and Perrott, MH. 2008. A Highly Digital MDLL-based Clock Multiplier that Leverages a Self-scrambling Time-to-digital Converter to Achieve Subpicosecond Jitter Performance. IEEE Journal of Solid-state Circuits, 43: 855–863.

View all references; Casha, Grech, Badets, Morche, and Micallef 20093. Casha, O, Grech, I, Badets, F, Morche, D and Micallef, J. 2009. Analysis of the Spur Characteristics of Edge-combining DLL-based Frequency Multipliers. IEEE Transactions on Circuits and Systems II: Express Briefs, 56: 132–136.

View all references). Consequently, several fully-digital implementations of PLLs reported in the literature (Chung and Lee 20035. Chung, C-C and Lee, C-Y. 2003. An All-digital Phase-locked Loop for High-speed Clock Generation. IEEE Journal of Solid-state Circuits, 38: 347–351.

View all references; Olsson and Nilsson 200415. Olsson, T and Nilsson, P. 2004. A Digitally Controlled PLL for SoC Applications. IEEE Journal of Solid-state Circuits, 39: 751–760.

View all references) aims noticeably at reducing the clock jitter. In Chung and Lee (20035. Chung, C-C and Lee, C-Y. 2003. An All-digital Phase-locked Loop for High-speed Clock Generation. IEEE Journal of Solid-state Circuits, 38: 347–351.

View all references), two digitally controlled oscillators (DCOs) are used to decrease the clock jitter. The first DCO is used for tracking the reference clock and the other is used for generating the output clock. However, the power consumption and chip area are greatly increased. In Olsson and Nilsson (200415. Olsson, T and Nilsson, P. 2004. A Digitally Controlled PLL for SoC Applications. IEEE Journal of Solid-state Circuits, 39: 751–760.

View all references), a time-to-digital converter (TDC) is utilised as a digital filter to increase the resolution of the phase error measurement and hence decrease the jitter. On the other hand, fully-digital implementations of DLLs suffer as well from two major drawbacks. First, the multiplication ratio depends mainly on the number of delay cells in the delay line. Second, any mismatch in the edge combining logic will be translated directly into a duty-cycle error and fixed-pattern jitter (Helal et al. 20088. Helal, BM, Straayer, MZ, Wei, G-Y and Perrott, MH. 2008. A Highly Digital MDLL-based Clock Multiplier that Leverages a Self-scrambling Time-to-digital Converter to Achieve Subpicosecond Jitter Performance. IEEE Journal of Solid-state Circuits, 43: 855–863.

View all references; Liang, Yang, and Liu 20089. Liang, C-K, Yang, R-J and Liu, S-I. 2008. An All-digital Fast-locking Programmable DLL-based Clock Generator. IEEE Transactions on Circuits and Systems I, Regular Papers, 55: 361–369.

View all references; Casha et al. 20093. Casha, O, Grech, I, Badets, F, Morche, D and Micallef, J. 2009. Analysis of the Spur Characteristics of Edge-combining DLL-based Frequency Multipliers. IEEE Transactions on Circuits and Systems II: Express Briefs, 56: 132–136.

View all references; Zlatanski, Uhring, Le Normand, and Mathiot 201117. Zlatanski, M, Uhring, W, Le Normand, J-P and Mathiot, D. 2011. A Fully Characterizable Asynchronous Multiphase Delay Generator. IEEE Transactions on Nuclear Science, 58: 418–425.

View all references). In this article, an FPGA-based design and implementation of a fully-digital wide-range programmable frequency synthesiser based on a digital finite state machine filter is presented. This paper is organized as follows. Section 2 describes the proposed architecture and Section 3 illustrates the key building blocks. Section 4 shows the circuit implementation and experimental results and Section 5 gives the conclusions.

The proposed architecture of the fully-digital frequency synthesiser circuit is shown in Figure 1. The circuit is composed of a frequency locked loop (FLL) and a delay locked loop (DLL) that share a common reference clock, F _REF. In summary, the FLL provides a frequency comparison through the frequency detector (FD) and hence maintains the frequency of the reference signal F _REF equal to the feedback signal (F _DCO/64), whereas the DLL leads to a phase locking (i.e. phases are equal or have a constant difference) between the output clock signal F _DCO and the input reference signal F _REF through the phase detector (PD). The proposed architecture provides the ability to select integer multiples of the reference signal frequency (e.g. F _REF, 2F _REF, 4F _REF, 8F _REF, 16F _REF, 32F _REF, and 64F _REF) that are synchronised to the reference clock signal.

The primary benefits of the proposed architecture are that it does not have the jitter accumulation issue of a PLL-based implementation as discussed earlier and the dual-loop architecture provides a more stable system (Ming-ta and Sobelman 200813. Ming-ta, H and Sobelman, G. 2008. Architectures for Multi-gigabit Wire-linked Clock and Data Recovery. IEEE Circuits and Systems Magazine, 8: 45–57.

View all references). The proposed circuit is portable and can be easily implemented for various platforms, such as FPGAs and integrated circuits, to get higher multiplication factor of the reference clock frequency. The frequency synthesizer circuit can be used as a part of SERDES devices in intra/inter chip communication in system-on-chip (SoC).

The basic operation of the frequency synthesiser circuit requires six key building blocks to provide frequency and phase locking.

The frequency synthesiser is totally designed using Verilog language and synthesized using Altera Quartus II Web Edition v11.0 software for Altera DE2-70 development board, with a Cyclone II EP2C35F672C6 FPGA on board. The DE2-70 board is equipped with 68416 logic elements (LEs). Using Quartus II software, the proposed architecture size is 1262 LEs (2%). The experimental setup consisting of the DE2-70 board, the Tektronix TDS-5104 digital phosphor oscilloscope, the ISO-TECH IGC2231 function generator, and the Advantest R3132 spectrum analyser is shown in Figure 6.

The frequency synthesiser has the ability to generate a clock signal of a range from 19.8 MHz to 440 MHz. Due to the frequency limitation of the function generator used, F_REF is limited to the range of 1.44–1.94 MHz and the two ring oscillator lengths L1 and L1+1 are set to be 5 and 6 respectively. M is set to be 255 and N varies from 0 to 255 and allows the DCO output frequency to be in the range of 92.6–124.2 MHz. The lowest N value gives the lowest DCO output frequency and vice versa. The measured output spectrums at N equal to 0 and 255 are shown in Figure 7. The DCO output frequency step is 0.12 MHz. The measured RMS and peak-to-peak jitter of the F _OUT signal is shown in Figure 8. The measured synchronization static phase offset at the F _OUT and F _REF signals is shown in Figure 9.

As shown in Table 1, different architectures of fully-digital frequency synthesizer circuits were synthesised for Altera DE2-70 development board and investigated in terms of maximum output frequency, area, frequency resolution, multiplication factor, power consumption, and portability. The power consumption is measured using Altera PowerPlay power analyser tool. The proposed architecture achieves the highest maximum output frequency as well as the highest multiplication factor. It has the ability to provide the smallest frequency steps, which means better frequency stability. As a disadvantage of the proposed architecture, the system occupies a large number of logic elements (LEs), and hence, its dynamic power consumption is relatively larger than the existing architectures. The large number of LEs is due to the architecture of the FLL controller block. It is composed of 255 states and each state represents a nine-bit value. Each bit is stored in a single D flip-flop. And hence, the FLL controller occupies 966 LEs (after Quartus II optimisation process). However, increasing the number of the states of the controller, gives higher frequency resolution (smaller frequency steps) at the expense of the architecture size.

A fully-digital wide-range programmable frequency synthesiser based on a finite state machine filter is presented in this article. The proposed architecture is totally designed using Verilog language and synthesized for Altera DE2-70 development board. Simulation and experimental results are included; they prove the synthesizing and tracking features of the proposed architecture. The generated clock signal frequency of a range from 19.8 MHz to 440 MHz is synchronized to the input reference clock with a frequency step of 0.12 MHz.