Design Methodology to Achieve Good Testability of VLSI Chips: An Industrial Perspective

Many of today’s Very Large Scale Integration
(VLSI) chips are digital design that has hundreds of
thousands to millions of transistors per chip. Testing of
such large VLSI chips proves to be a challenge. One
method of addressing this challenge is the introduction of
Design For Test (DFT) features into the VLSI chips. This
paper describes an efficient methodology of achieving
good testability of VLSI chip using a combination of
Register Transfer Level (RTL) coding styles with full
scan chain implementation and Automatic Test Pattern
Generation (ATPG). This paper also describes the method
of sharing of DFT pins associated with scan chain in order
to reduce packaging cost due to DFT.