Resistance dependent delay behaviour of resistive open faults in multi voltage designs

Multi-voltage designs are becoming omnipresent in most of state-of-the-art battery powered portable devices. Understanding the fault behaviour in multi-voltage environment helps in testing such devices for voltage dependent manufacturing faults. Resistive open fault is a major class of such faults, therefore in this paper, we studied its behaviour (manifested as extra delay) in multi-voltage like environment. The extra delay caused by resistive open faults versus voltage is analysed for the full range of open resistance. It is showed that the pattern of this delay as a function of VDD is resistance dependent. This observation was validated using a set of benchmark circuits and technology models. Based on this observation, we proposed treating the full range of opens resistances as smaller subsets of resistance intervals according to the behaviour manifested.