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Design & simulation of an improved soft-switched synchronous buck converter

N.Z., Yahaya and K.M., Begam and M., Awan (2009) Design & simulation of an improved soft-switched synchronous buck converter. In: 2009 3rd Asia International Conference on Modelling and Simulation, AMS 2009, 25 May 2009 through 26 May 2009, Bandung, Bali.

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Abstract

This paper proposes an improved soft switched synchronous buck converter in a fixed load condition. The switching energy can be fully recovered during current commutation phase in the gate driver while the diode conduction losses in the low and high side switches can be substantially reduced by employing additional L and C resonant in the circuit. Using PSpice simulation, the optimization technique has been studied. From the predetermined pulse width of the generated signals, the optimized resonant inductor current is observed to generate less oscillation and hence lower the switching loss. In addition, an optimized dead time interval is inserted between high side and low side of the transistors in the synchronous buck converter to minimize their body diode conduction losses. The detailed operations of both circuits are analyzed. © 2009 IEEE.

Item Type:Conference or Workshop Item (Paper)
Uncontrolled Keywords:Body-diode conduction; Conduction loss; Current commutation; Dead time; Gate drivers; High-side switch; Load condition; Optimization techniques; PSpice simulation; Pulse width; Resonant gate driver; Resonant inductors; Switching energy; Switching loss; Synchronous buck converter; ZVS; Automobile drivers; Optimization; Soft switching; SPICE; Zero voltage switching
Subjects:Q Science > Q Science (General)
Q Science > QA Mathematics > QA75 Electronic computers. Computer science
Departments / MOR / COE:Departments > Computer Information Sciences
ID Code:94
Deposited By: Dr Nor Zaihar Yahaya
Deposited On:23 Feb 2010 04:07
Last Modified:19 Jan 2017 08:25

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