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An Improved Markov Random Field Design Approach For Digital Circuits: Introducing Fault-Tolerance With Higher Noise-Immunity For The Nano-Circuits As Compared To CMOS And MRF Designs Zoom See larger image (with zoom) Share your own customer images Publisher: learn how customers can search inside this book. An Improved Markov Random Field Design Approach For Digital Circuits: Introducing Fault-Tolerance With Higher Noise-Immunity For The Nano-Circuits As Compared To CMOS And MRF Designs

Anwer, Janhanzeb and Hamid, Nor Hisham and Asirvadam , Vijanth Sagayan (2011) An Improved Markov Random Field Design Approach For Digital Circuits: Introducing Fault-Tolerance With Higher Noise-Immunity For The Nano-Circuits As Compared To CMOS And MRF Designs Zoom See larger image (with zoom) Share your own customer images Publisher: learn how customers can search inside this book. An Improved Markov Random Field Design Approach For Digital Circuits: Introducing Fault-Tolerance With Higher Noise-Immunity For The Nano-Circuits As Compared To CMOS And MRF Designs. LAP LAMBERT Academic Publishing, Germany. ISBN 978-3844332636

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Abstract

As the MOSFET dimensions scale down to nanoscale level, the reliability of circuits based on these devices decreases. Therefore, a mechanism has to be devised that can make the nanoscale systems perform reliably using unreliable circuit components. The solution is fault-tolerant circuit design. Markov Random Field (MRF) is an effective approach that achieves fault-tolerance in integrated circuit design. The previous research on this technique suffers from limitations at the design, simulation and implementation levels. As improvements, the MRF fault-tolerance rules have been validated for a practical circuit example. The simulation framework is extended from thermal to a combination of thermal and random telegraph signal noise sources to provide a more rigorous noise environment for the simulation of nanoscale circuits. Moreover, an architecture-level improvement has been proposed in the design of previous MRF gates. The re-designed MRF is termed as Improved-MRF. By simulating various test circuits in Cadence, it is found that Improved-MRF circuits are 400 whereas MRF circuits are only 10 times more noise-tolerant than the CMOS alternatives.

Item Type:Book
Subjects:T Technology > TK Electrical engineering. Electronics Nuclear engineering
Q Science > QA Mathematics > QA75 Electronic computers. Computer science
Departments / MOR / COE:Centre of Excellence > Center for Intelligent Signal and Imaging Research
Departments > Electrical & Electronic Engineering
ID Code:6904
Deposited By: Dr Vijanth Sagayan Asirvadam
Deposited On:05 Dec 2011 03:01
Last Modified:29 Mar 2014 19:01

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