SWITCHING LOSS ANALYSIS OF A DIODE-CLAMPED RESONANT GATE DRIVER NETWORK

This paper is about the analysis of switching losses in a diode-clamped resonant gate driver network. The LC configuration of this network is studied to explore the limitations of resonant current based on the inductance values. With fixed capacitance value from the internal power transistor device, the switching losses within the gate driver circuit are evaluated in search for optimization purposes. It is found that there are limitations in the inductance value and the duty ratio from the influence of dead time for all the inductance values. Where dead time must be provided to avoid the shoot-through within the totem-poled configuration switches, this presents the trade-offs between the dead time, inductance value and duty ratio generation which are discussed in detail. PSpice circuit simulator is employed in the study using 1 MHz switching frequency. The results show remarkable findings which draw new limitations and suggest ways for the synchronous rectifier circuit design.