Logo

Design Methodology to Achieve Good Testability of VLSI Chips: An Industrial Perspective

Lo, Hai Hiung and Lee, Weng Fook and Reaz, B. I. and Hamid, Nor Hisham (2009) Design Methodology to Achieve Good Testability of VLSI Chips: An Industrial Perspective. In: International Conference on Electronic Design (ICED 2008), 1~3 December, 2008, Park Royal Hotel, Penang, Malaysia.

[img] PDF - Published Version
Restricted to Registered users only

298b

Abstract

Many of today’s Very Large Scale Integration (VLSI) chips are digital design that has hundreds of thousands to millions of transistors per chip. Testing of such large VLSI chips proves to be a challenge. One method of addressing this challenge is the introduction of Design For Test (DFT) features into the VLSI chips. This paper describes an efficient methodology of achieving good testability of VLSI chip using a combination of Register Transfer Level (RTL) coding styles with full scan chain implementation and Automatic Test Pattern Generation (ATPG). This paper also describes the method of sharing of DFT pins associated with scan chain in order to reduce packaging cost due to DFT.

Item Type:Conference or Workshop Item (Paper)
Subjects:T Technology > TK Electrical engineering. Electronics Nuclear engineering
Departments / MOR / COE:Departments > Electrical & Electronic Engineering
ID Code:5340
Deposited By: Mr Hai Hiung Lo
Deposited On:04 Apr 2011 05:32
Last Modified:19 Jan 2017 08:25

Repository Staff Only: item control page

Document Downloads

More statistics for this item...