A Performance Comparison Study on Multiplier Designs

Lee, Chris Y. H. and Lo, H. H. and Lee, Sean, W. F. and Hamid, Nor Hisham (2010) A Performance Comparison Study on Multiplier Designs. Proceedings International Conference of Intelligent and Advanced System .

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This study investigates the relative performances of Array, Wallace, Dadda and Reduced Area multipliers for several synthesis optimization modes. All multiplier designs were modeled in Verilog HDL and synthesized based on the TSMC 0.35-micron ASIC Design Kit standard cell library. Performance data was extracted after logic synthesis in LeonardoSpectrum for Area, Speed and Auto optimization modes. Findings indicate that the Dadda multiplier may not always have a speed advantage over Wallace’s design, but depends greatly on the optimization effects in gate-level synthesized design. Results for comparison of 32x32-bit variants indicate that the Wallace scheme is well suited for high-speed applications, independent of area constraints, while the Dadda and Reduced Area designs deliver best speed when synthesized to minimize area or logic usage.

Item Type:Article
Subjects:T Technology > TK Electrical engineering. Electronics Nuclear engineering
Departments / MOR / COE:Departments > Electrical & Electronic Engineering
ID Code:4988
Deposited By: Mr Hai Hiung Lo
Deposited On:23 Mar 2011 05:00
Last Modified:19 Jan 2017 08:24

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