Delay Fault Modelling/Simulation using VHDL-AMS in Multi Vdd Systems

Zain Ali, Noohul Basheer and Mark, Zwolinski and Ahmadi, Arash (2008) Delay Fault Modelling/Simulation using VHDL-AMS in Multi Vdd Systems. In: PROC. 26th INTERNATIONAL CONFERENCE ON MICROELECTRONICS (MIEL 2008), 11-14 May, 2008, Nis, Serbia.

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With the growing density of Very Large Scale Integrated(VLSI circuits, traditional digital fault simulation is no longer a viable option. This is because of analogue-like behaviour in digital circuits. The need for fast fault simulation is one of the main requirements in test pattern generation. The trade off between accurate simulations at transistor level, as in SPICE and fast simulationat gate level using a Hardware Descriptive Language(HDL)can be achieved by using behavioural modelling languages such as VHDL-AMS. In this paper, we have demonstrated that behavioural fault simulation for resistive faults can produce fast and accurate results.

Item Type:Conference or Workshop Item (Lecture)
Subjects:T Technology > TK Electrical engineering. Electronics Nuclear engineering
Departments / MOR / COE:Departments > Electrical & Electronic Engineering
ID Code:4806
Deposited By: Dr Noohul Basheer Zain Ali
Deposited On:23 Mar 2011 05:42
Last Modified:19 Jan 2017 08:26

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