A Case Study for Reliability-Aware in SoC Analog Circuit Design

This paper provides a working knowledge of
Negative Bias Temperature Instability (NBTI) awareness to the circuit design community for reliable design of the System-Ona-Chip (SoC) analog circuit. The reliability performance of all matched pair circuits, such as Bandgap Reference, is at the mercy of aging differential. Aging simulation (AgingSim) is mandatory to obtain realistic risk evaluation for circuit design reliability qualification. It is applicable to all circuit aging problems covering both analog and digital. Failure rate varies as a function of voltage and temperature. It is shown that PMOS is the reliability-critical device and NBTI is the most critical failure mechanism for analog circuit performance in sub-micrometer CMOS technology. We provide a complete reliability simulation analysis of Thermal Sensor DAC and analyze the effect of NBTI using aging simulation tool.