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Computation and analysis of output error probability for C17 benchmark circuit using bayesian networks error modeling

Khalid, U. and Anwer, J. and Singh, N. and Hamid, N.H. and Asirvadam, V.S. (2010) Computation and analysis of output error probability for C17 benchmark circuit using bayesian networks error modeling. In: Research and Development (SCOReD), 2010 IEEE Student Conference on.

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Abstract

The reliability of digital circuits is in question since the new scaled transistor technologies continue to emerge. The major factor deteriorating the circuit performance is the random and dynamic nature of errors encountered during its operation. Output-error probability is the direct measure of circuit's reliability. Bayesian networks error modeling is the approach used to compute error probability of digital circuits. In our paper, we have used this technique to compute and analyze the output error probability of LGSynth's C17 benchmark circuit. The simulations are based on MATLAB and show important relationships among output-error probability, execution time and number of priors involved in the analysis.

Item Type:Conference or Workshop Item (Paper)
Uncontrolled Keywords:Bayesian network error modeling;C17 benchmark circuit;MATLAB;digital circuit reliability;execution time;output error probability;output-error probability;circuit reliability;error statistics;
Subjects:T Technology > TK Electrical engineering. Electronics Nuclear engineering
Departments / MOR / COE:Departments > Electrical & Electronic Engineering
ID Code:4635
Deposited By: Dr Vijanth Sagayan Asirvadam
Deposited On:22 Nov 2012 02:55
Last Modified:19 Jan 2017 08:23

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