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The Study of Q-Factor in High Frequency Diode-Clamped Resonant Gate Driver Circuit

Yahaya, Nor Zaihar and rupadi, norazrin (2009) The Study of Q-Factor in High Frequency Diode-Clamped Resonant Gate Driver Circuit. Proceedings of the 2nd Seminar on Engineering and Information Technology . pp. 3-7. ISSN Proceedings of the 2nd Seminar on Engineering and Information Technology

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Abstract

The analysis of Q-factor in high frequency resonant gate driver circuit is presented in this work. It is based on the variation of resonant inductor values in the diode-clamped resonant gate driver circuit. At high switching frequency, a lower value of inductance is preferred. However this will result in lower Q and high gate resistance power loss. On the other hand, at higher inductance, gate resistance power loss reduces but this increases dissipation on the switch. Due to the fact that Q-factor depends on circuit topology and power switches, it has become an indicator towards gate driver’s performance. It is found that Q is optimized at 0.83 for 18 nH, having satisfied the design inequality equation with lower switching loss and less oscillation at the switch’s gate voltage. The simulation work has been carried out using the PSpice simulation software for 1 MHz switching frequency. Details of simulation analysis are discussed in the paper.

Item Type:Article
Subjects:T Technology > TK Electrical engineering. Electronics Nuclear engineering
Departments / MOR / COE:Departments > Electrical & Electronic Engineering
ID Code:4393
Deposited By: Dr Nor Zaihar Yahaya
Deposited On:14 Mar 2011 08:58
Last Modified:19 Jan 2017 08:25

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