Design & Simulation of an Improved Soft-switched Synchronous Buck Converter

This paper proposes an improved soft switched
synchronous buck converter in a fixed load condition.
The switching energy can be fully recovered during
current commutation phase in the gate driver while the
diode conduction losses in the low and high side
switches can be substantially reduced by employing
additional L and C resonant in the circuit. Using PSpice
simulation, the optimization technique has been studied.
From the predetermined pulse width of the generated
signals, the optimized resonant inductor current is
observed to generate less oscillation and hence lower
the switching loss. In addition, an optimized dead time
interval is inserted between high side and low side of the
transistors in the synchronous buck converter to
minimize their body diode conduction losses. The
detailed operations of both circuits are analyzed.