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Hardware Implementation of an Optimized Processor Architecture for SOBEL Image Edge Detection Operator

M. Osman, Zahraa Elhassan and Hussin, Fawnizu Azmadi and Zain Ali, Noohul Basheer (2010) Hardware Implementation of an Optimized Processor Architecture for SOBEL Image Edge Detection Operator. In: International Conference on Intelligent and Advanced Systems (ICIAS 2010), 15-17 June, 2010, Kuala Lumpur, Malaysia.

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Abstract

This paper presents an implementation of a dedicated processor for image edge detection on field programmable gate arrays (FPGAs). The processor architecture is originally a Sobel based edge detection filter optimized to minimize memory utilization, redundant calculations and hence, overall logic resources used to implement the processor on FPGA. The optimization is achieved by exploiting the FPGAs' high parallelism, flexibility and I/O bandwidth. Results show that our optimized processor architecture uses 22% less Adaptive Lookup Tables (ALUTs) 40% less dedicated logic registers and 10% overall logic resources utilization reduction over basic architecture in [1] when implemented on Stratix II EP2S60. The optimization makes the processor feasible to be used for applications like embedded video processing.

Item Type:Conference or Workshop Item (Paper)
Subjects:T Technology > TK Electrical engineering. Electronics Nuclear engineering
Departments / MOR / COE:Departments > Electrical & Electronic Engineering
ID Code:4235
Deposited By: Dr Fawnizu Azmadi Hussin
Deposited On:14 Feb 2011 06:43
Last Modified:19 Jan 2017 08:24

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