Koko I., Saeed and H., Agustiawan (2009) Parallel form of the pipelined intermediate architecture for two-dimensional discrete wavelet transform. [Citation Index Journal]
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Abstract
A lifting-based VLSI architecture for two-dimensional discrete wavelet transform (2-D DWT) for 5/3 and 9/7 algorithms, called, pipelined intermediate architecture was proposed by Ibrahim et al., which aim at reducing power consumption of the overlapped external memory access without using the expensive line-buffer. In this paper, we explore parallelism in order to best meet real-time applications of 2-D DWT with demanding requirements in terms of speed, throughput, and power consumption. Therefore, 2-parallel and 3-parallel form of the single pipelined intermediate architecture are proposed. The 2-parallel and 3-parallel pipelined intermediate architectures achieve speedup factors of 2 and 3, respectively, as compared with single pipelined intermediate architecture proposed by Ibrahim et al.
Item Type: | Citation Index Journal |
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Uncontrolled Keywords: | Discrete wavelet transform; Lifting scheme; Parallel intermediate architecture; VLSI |
Subjects: | T Technology > TK Electrical engineering. Electronics Nuclear engineering |
Departments / MOR / COE: | Departments > Electrical & Electronic Engineering |
ID Code: | 417 |
Deposited By: | Mr Helmi Iskandar Suito |
Deposited On: | 09 Mar 2010 01:09 |
Last Modified: | 19 Jan 2017 08:25 |
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