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Scheduling Power-Constrained Tests through the SoC Functional Bus

Hussin, Fawnizu Azmadi and Yoneda, Tomokazu and Orailoglu, Alex and Fujiwara, Hideo (2008) Scheduling Power-Constrained Tests through the SoC Functional Bus. Transactions on Information and Systems, Volume (Issue ). pp. 736-746. ISSN 0916-8532

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Abstract

This paper proposes a test methodology for core-based testing of System-on-Chips by utilizing the functional bus as a test access mechanism. The functional bus is used as a transportation channel for the test stimuli and responses from a tester to the cores under test (CUT). To enable test concurrency, local test buffers are added to all CUTs. In order to limit the buffer area overhead while minimizing the test application time, we propose a packet-based scheduling algorithm called PAcket Set Scheduling (PASS), which finds the complete packet delivery schedule under a given power constraint. The utilization of test packets, consisting of a small number of bits of test data, for test data delivery allow an efficient sharing of bus bandwidth with the help of an effective buffer-based test architecture. The experimental results show that the methodology is highly effective, especially for smaller bus widths, compared to previous approaches that do not use the functional bus.

Item Type:Article
Subjects:T Technology > TK Electrical engineering. Electronics Nuclear engineering
Departments / MOR / COE:Departments > Electrical & Electronic Engineering
ID Code:3594
Deposited By: Dr Fawnizu Azmadi Hussin
Deposited On:23 Dec 2010 08:46
Last Modified:19 Jan 2017 08:26

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