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Power-Constrained SOC Test Schedules through Utilization of Functional Buses

Hussin, Fawnizu Azmadi and Yoneda, Tomokazu and Orailoglu, Alex and Fujiwara, Hideo (2006) Power-Constrained SOC Test Schedules through Utilization of Functional Buses. In: IEEE International Conference on Computer Design (ICCD'06), 1-4 October 2006, San Jose, USA.

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Abstract

In this paper, we are proposing a core-based test methodology that utilizes the functional bus for test stimuli and response transportation. An efficient algorithm for the generation of a complete test schedule that efficiently utilizes the functional bus under a power constraint is described. The test schedule is composed of a set of test vector delivery sequences in small chunks, denoted as packets. The utilization of small packet sizes optimizes the functional bus utilization. The experimental results show that the methodology is highly effective compared to previous approaches that do not use the functional bus. The strong results of the proposed approach are particularly highlighted when small bus widths are considered, an important consideration in current SOC designs where increasingly larger bus widths pose routing and reliability challenges.

Item Type:Conference or Workshop Item (Paper)
Subjects:T Technology > TK Electrical engineering. Electronics Nuclear engineering
Departments / MOR / COE:Departments > Electrical & Electronic Engineering
ID Code:3593
Deposited By: Dr Fawnizu Azmadi Hussin
Deposited On:23 Dec 2010 08:43
Last Modified:19 Jan 2017 08:27

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