RedSOCs‐3D: Thermal‐safe Test Scheduling for 3D‐Stacked SoC

Hussin, Fawnizu Azmadi and Yu, Thomas Edison Chua and Yoneda, Tomokazu and Fujiwara, Hideo (2010) RedSOCs‐3D: Thermal‐safe Test Scheduling for 3D‐Stacked SoC. In: 2010 IEEE Asia Pacific Conference on Circuits and Systems, 6-9 December, 2010, Kuala Lumpur, Malaysia.

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This paper investigates the challenges of a 3D-stacked system-on-chip testing, especially in terms of thermal problem. It is known that test power can be more than twice the intended power dissipation of the chip in the functional mode, for a single die. This problem is exacerbated when more than one dies are stacked on top of each other in a single package. Without proper test strategies, the thermal limit could be exceeded during test and this could permanently damage the possibly good chips. Using a heuristic approach, we proposed a set of rules that need to be followed when scheduling the core tests of each chip layer. These rules are based on the initial findings of 3D-chip test simulation using a commercial thermal simulation tool. Using these simple rules, it was found that up to 40% reduction in the peak temperature can be achieved when the thermal-aware test scheduling technique is employed.

Item Type:Conference or Workshop Item (Paper)
Subjects:T Technology > TK Electrical engineering. Electronics Nuclear engineering
Departments / MOR / COE:Departments > Electrical & Electronic Engineering
ID Code:3559
Deposited By: Dr Fawnizu Azmadi Hussin
Deposited On:20 Dec 2010 06:59
Last Modified:19 Jan 2017 08:23

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