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CMOS IC Design and Verilog-A Modelling of 10-Gb/s PLL-Based Deserializer for Inter-Chip Communication in SOC

Assaad, Maher (2007) CMOS IC Design and Verilog-A Modelling of 10-Gb/s PLL-Based Deserializer for Inter-Chip Communication in SOC. In: International Symposium on System on Chip.

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Item Type:Conference or Workshop Item (Paper)
Subjects:T Technology > TK Electrical engineering. Electronics Nuclear engineering
Departments / MOR / COE:Centre of Excellence > Center for Intelligent Signal and Imaging Research
Departments > Electrical & Electronic Engineering
ID Code:3503
Deposited By: Dr Maher Assaad
Deposited On:04 Jan 2011 07:47
Last Modified:19 Jan 2017 08:27

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