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Optimization of Processor Architecture for Image Edge Detection Filter

M. Osman, Zahraa Elhassan and Hussin, Fawnizu Azmadi and Zain Ali, Noohul Basheer (2010) Optimization of Processor Architecture for Image Edge Detection Filter. In: 12th International Conference on Modelling and Simulation (UMSim), 24-26 March 2010, Cambdridge, UK.

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Official URL: http://dx.doi.org/10.1109/UKSIM.2010.123

Abstract

In this paper, a dedicated edge detection processor architecture based on field programmable gate arrays is presented. The architecture is an optimization of the Sobel edge detection filter, specifically focusing on the reduction of the computation time. The proposed architecture reduces the number of calculations required for the edge detection process by enhancing the data reuse, i.e. minimizing the frequency of memory access. Direct hardware implementation as proposed by previous works require most image pixels to be read from memory up to six times and transferred into the Sobel edge detection processor. In our work, we try to reduce the number of pixels read therefore affecting tremendous potential speed suitable for the embedded video processing applications.

Item Type:Conference or Workshop Item (Paper)
Subjects:Q Science > QA Mathematics > QA75 Electronic computers. Computer science
Academic Subject One:Academic Department - Electrical And Electronics - Pervasisve Systems - Digital Electronics - Programmable Devices
Departments / MOR / COE:Centre of Excellence > Center for Intelligent Signal and Imaging Research
Departments > Electrical & Electronic Engineering
Research Institutes > Institute for Health Analytics
ID Code:2089
Deposited By: Dr Fawnizu Azmadi Hussin
Deposited On:10 May 2010 10:54
Last Modified:19 Jan 2017 08:24

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