A Case Study of Process Variation Effect to SoC Analog Circuits

Latif, Mohd Azman Abdul and Zain Ali, Noohul Basheer and Hussin, Fawnizu Azmadi (2011) A Case Study of Process Variation Effect to SoC Analog Circuits. In: IEEE Recent Advances in Intelligent Computational Systems, Sep 22-24,2011, Trivandrum, India.

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Recent submicron process technology scaling leads the urgency to build an efficient methodology of characterizing and modeling the process variation effect, for example, the threshold voltage, Vt. This is one of the key process parameters that must be extensively modeled and validated for accurate circuit performance. Furthermore, this requirement is even much more critical for analog applications which demand an ability to match devices precisely. Analog circuits use larger device dimensions as compared to digital circuits in order to minimize the process variation implication. This has led Negative Bias Temperature Instability (NBTI) to be the most performance limiter compared to the rest of reliability mechanisms. This reliability sensitivity is even more challenging as most of the circuit blocks (digital and analog) are fabricated on the same chip for system-on-chip (SoC) applications. This paper will describe in detail the actions taken to minimize impact to customers and will show how important proper aging simulations to be conducted with the right combination of process, voltage, temperature (PVT) and coupling/timing to occur due to process variation effect beyond specifications on analog differential amplifier (diffamp) circuits in SoC products.

Item Type:Conference or Workshop Item (Paper)
Academic Subject One:Academic Department - Electrical And Electronics - Pervasisve Systems - Digital Electronics - System on Chip (SoC)
Departments / MOR / COE:Centre of Excellence > Center for Intelligent Signal and Imaging Research
ID Code:11996
Deposited By: Dr Fawnizu Azmadi Hussin
Deposited On:07 Oct 2016 01:42
Last Modified:19 Jan 2017 08:23

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