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Propagation of delay faults caused by resistive open faults with dynamic voltage scaling awareness

Mohammadat, Mohamed Tag Elsir and Zain Ali, Noohul Basheer and Hussin, Fawnizu Azmadi (2011) Propagation of delay faults caused by resistive open faults with dynamic voltage scaling awareness. In: 3rd National Postgraduate Conference, 19-20 September 2011, Universiti Teknologi PETRONAS, Perak, Malaysia.

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Abstract

Fault Diagnosis is important step in detecting manufacturing process problems and improving its quality. Characterizing the effect of faults on the performance of circuits is essential in diagnosing and testing faulty chips. Resistive opens are common manufacturing faults which affect the timing performance of circuits. In dynamic voltage scaling environment, the supply voltage and clock frequency are dynamically adjusted to meet the processing demands. With this awareness, we previously demonstrated that the delay caused by resistive opens as the VDD increases show different increment and decrement patterns depending on the range of the open resistance value. However, the path delay in CMOS circuits increases exponentially with reduced VDD. In this work, we investigate how the delay of the opens is propagated through the CMOS circuit. We show how this behavior is manifested with the aid of simulation on benchmark circuits based on 130nm technology model as well as 65nm, 22nm and 16nm Berkeley Predictive Technology Models (BPTM). Based on this observation and to ease fault related work on resistive open faults, we proposed dividing the full range of opens resistances into smaller subsets of resistance intervals.

Item Type:Conference or Workshop Item (Paper)
Academic Subject One:Academic Department - Electrical And Electronics - Pervasisve Systems - Digital Electronics - Test and Reliablity
Departments / MOR / COE:Centre of Excellence > Center for Intelligent Signal and Imaging Research
ID Code:11995
Deposited By: Dr Fawnizu Azmadi Hussin
Deposited On:07 Oct 2016 01:42
Last Modified:19 Jan 2017 08:23

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