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High rate (3, k) regular LDPC encoder architecture

Anggraeni, Silvia and Hussin, Fawnizu Azmadi and Jeoti , Varun (2011) High rate (3, k) regular LDPC encoder architecture. In: 3rd National Postgraduate Conference, 19-20 September 2011, Universiti Teknologi PETRONAS, Perak, Malaysia.

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Abstract

This paper highlights recent developments in low density parity check (LDPC) encoder. There are some parameters applied in LDPC encoder such as type of LDPC codes, code length, code rate and encoding method. We emphasize that no attempts have been made for the implementation of (3, k) regular LDPC encoder with high code rate (R ≥ 0.875) and few works on flexible LDPC encoder which accommodates various code rates and code lengths. Therefore, this paper proposes a high rate (3, k) regular LDPC encoder architecture which is suitable for high code rate (R ≥ 0.875) applications. Division of workloads between stages is built based on the number of non-zero elements in the parity check matrix (H).

Item Type:Conference or Workshop Item (Paper)
Academic Subject One:Academic Department - Electrical And Electronics - Pervasisve Systems - Digital Electronics - Design
Departments / MOR / COE:Centre of Excellence > Center for Intelligent Signal and Imaging Research
ID Code:11994
Deposited By: Dr Fawnizu Azmadi Hussin
Deposited On:07 Oct 2016 01:42
Last Modified:19 Jan 2017 08:23

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