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Design and FPGA Implementation of PLL-based Quarter-rate Clock and Data Recovery Circuit

Alser, Mohammed and Assaad, Maher and Hussin, Fawnizu Azmadi and Bayou, Israel Yohannes (2012) Design and FPGA Implementation of PLL-based Quarter-rate Clock and Data Recovery Circuit. In: 4th International Conference on Intelligent and Advanced Systems (ICIAS 2012), 12-14 June 2012, Kuala Lumpur.

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Abstract

This paper overviews the increased dynamic power consumption issue associated with the use of the serial links as a medium of data communication in today's multi-module based system-on-chip (SoC) and presents a novel all-digital PLL-based quarter-rate clock and data recovery circuit as a potential solution. The proposed architecture works at a frequency equal to one-fourth the received data rate and utilizes a quarter-rate early-late type phase detector, a delay line, a delay line controller, and a digitally controlled oscillator (DCO)-based 8-phases generator. The proposed architecture can be adapted easily for different FPGA families, as well as implemented as an integrated circuit. Moreover, it can be used in a deserializer as part of a SERDES in inter-module communication in SoC. The proposed architecture is designed using the Verilog language and synthesized for the Altera DE2-70 development board. Furthermore, the simulation results validate the expected functionality, such as performing quarter-rate phase detection as well as 1-to-4 demultiplexing. The synthesized design requires 117 logic elements using the above Altera board.

Item Type:Conference or Workshop Item (Paper)
Academic Subject One:Academic Department - Electrical And Electronics - Pervasisve Systems - Digital Electronics - Embedded Systems
Departments / MOR / COE:Centre of Excellence > Center for Intelligent Signal and Imaging Research
ID Code:11988
Deposited By: Dr Fawnizu Azmadi Hussin
Deposited On:07 Oct 2016 01:42
Last Modified:19 Jan 2017 08:21

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