High Throughput Architecture for Low Density Parity Check (LDPC) Encoder

Anggraeni, Silvia and Hussin, Fawnizu Azmadi and Jeoti , Varun (2013) High Throughput Architecture for Low Density Parity Check (LDPC) Encoder. In: IEEE 56th Midwest Symposium on Circuits & Systems (MWSCAS 2013), 4-7 August 2013, Ohio, USA.

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This paper proposes a bit-wise matrix-vector multiplication in the optimization of a proposed low density parity check (LDPC) encoder. Investigation of this proposed architecture is done by implementing five code lengths using one IEEE 802.16e standard code rate. It is shown that the proposed architecture outperforms other works in terms of information throughput ranging from 0.235 to 8.83 times higher. In term of ratio of throughput per area, the proposed method exceeds other works in the range of 1.19 to 6.54 times higher.

Item Type:Conference or Workshop Item (Paper)
Academic Subject One:Academic Department - Electrical And Electronics - Pervasisve Systems - Digital Electronics - Design
Departments / MOR / COE:Centre of Excellence > Center for Intelligent Signal and Imaging Research
ID Code:11981
Deposited By: Dr Fawnizu Azmadi Hussin
Deposited On:07 Oct 2016 01:42
Last Modified:19 Jan 2017 08:21

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