Logo

Optimized Encoder Architecture for Structured Low Density Parity Check Codes of Short Length

Anggraeni, Silvia and Hussin, Fawnizu Azmadi and Jeoti , Varun (2014) Optimized Encoder Architecture for Structured Low Density Parity Check Codes of Short Length. In: 5th International Conference on Intelligent and Advanced Systems, ICIAS 2014, 3-5 June 2014, Kuala Lumpur Malaysia.

[img] PDF - Published Version
Restricted to Registered users only

209Kb

Abstract

This paper proposes an architecture for structured low density parity check encoder. The proposed architecture supports the limitation of input/output pins of field programmable gate array using division of information bits. The division of information bits generates latency of encoding. The proposed architecture does not store the required matrix for bit-wise multiplication and does not use cyclic shift of barrel shifter. The proposed architecture is investigated using code length below 1000 bits and implementation of high code rate R = 5/6 and code length between 1000 and 2000 bits. Even though this architecture is optimized for short code length, it is shown that the proposed architecture achieves information throughput of 30.178 Gbps and area of 2737 logic element when code length N = 1944 and code rate R = 5/6.

Item Type:Conference or Workshop Item (Paper)
Academic Subject One:Academic Department - Electrical And Electronics - Pervasisve Systems - Digital Electronics - Design
Departments / MOR / COE:Centre of Excellence > Center for Intelligent Signal and Imaging Research
ID Code:11965
Deposited By: Dr Fawnizu Azmadi Hussin
Deposited On:07 Oct 2016 01:42
Last Modified:19 Jan 2017 08:21

Repository Staff Only: item control page

Document Downloads

More statistics for this item...