Bio-inspired NoC fault tolerant techniques

Sethi, Muhammad Athar Javed and Hussin, Fawnizu Azmadi and Hamid, Nor Hisham (2014) Bio-inspired NoC fault tolerant techniques. In: International Conference On Intelligent & Advanced Systems (ICIAS 2014), 3-5 June 2014, Kuala Lumpur, Malaysia.

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The incorporation of processing elements which include processor cores, memories, configurable components and DSP cores on Network on Chip (NoC) have made the communication structure of NoC very complex. To support the complexity of NoC, the physical device sizes are scaled down. However, the interconnects are not scaled at the same rate as the device. Interconnects have contributed to faults, system delay and high power consumptions. Interconnects of NoC are more vulnerable to faults. Many fault tolerant routing techniques have been proposed but they still have the energy, power, congestion problems and they lack the adaptiveness and robustness. In this work, two novel bio-inspired NoC techniques are analyzed. The bio-inspired mechanism of “synaptogenesis” and “sprouting” is adopted in the NoC algorithm and architecture. With the help of this the algorithm is robust and NoC is fault tolerant. In sprouting algorithm, the average throughput and average packet latency was increased by 8.56% and 4.65% respectively while average bandwidth was efficiently utilized by 0.23% as compared to synaptogenesis algorithm. The bio-inspired algorithms improved the average throughput and accepted traffic by 72.12% as compared to the literature technique.

Item Type:Conference or Workshop Item (Paper)
Academic Subject One:Academic Department - Electrical And Electronics - Pervasisve Systems - Digital Electronics - System on Chip (SoC)
Departments / MOR / COE:Centre of Excellence > Center for Intelligent Signal and Imaging Research
ID Code:11964
Deposited By: Dr Fawnizu Azmadi Hussin
Deposited On:07 Oct 2016 01:42
Last Modified:19 Jan 2017 08:21

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