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Automatic generation of test instructions for path delay faults based-on stuck-at fault in processor cores using assignment decision diagram

Shaheen, Ateeq-Ur-Rehman and Hussin, Fawnizu Azmadi and Hamid, Nor Hisham and Zain Ali, Noohul Basheer (2014) Automatic generation of test instructions for path delay faults based-on stuck-at fault in processor cores using assignment decision diagram. In: 5th International Conference On Intelligent & Advanced Systems (ICIAS 2014), 3-5 June 2014, Kuala Lumpur Malaysia.

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Abstract

Instruction execution from the cache to detect the faulty chips in native mode has proven its effectiveness with high performance and low power consumption. Gate-level ATPG are time expensive and difficult to implement for large design. In this paper, we proposed an RTL-based methodology framework to generate the test program based on instructions set architecture (ISA) to test structural faults in processor cores. The proposed methodology framework made three major contributions. First, the use of effective conjunctive normal formula (CNF) encoding and instruction set architecture (ISA) prunes the combinational and sequential search space. Second, the modular based test generation and use of instruction set architecture (ISA) considerably reduces the test generation time. Third, an automatic generation of test instructions for structural faults.

Item Type:Conference or Workshop Item (Paper)
Academic Subject One:Academic Department - Electrical And Electronics - Pervasisve Systems - Digital Electronics - Test and Reliablity
Departments / MOR / COE:Centre of Excellence > Center for Intelligent Signal and Imaging Research
ID Code:11963
Deposited By: Dr Fawnizu Azmadi Hussin
Deposited On:07 Oct 2016 01:42
Last Modified:19 Jan 2017 08:21

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