Optimization of Processor Architecture for Sobel Real-Time Edge Detection Using FPGA

Hussin, Fawnizu Azmadi and Osman, Zahraa E. M. and Xia, Likun and Zain Ali, Noohul Basheer (2013) Optimization of Processor Architecture for Sobel Real-Time Edge Detection Using FPGA. International Review on Computers and Software (IRECOS), 8 (4). ISSN 1828-6011

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This paper presents an optimized processor architecture for Sobel edge detection operator on field programmable gate arrays (FPGA). The processor is optimized by the use of several optimization techniques that aim to increase the processor throughput and reduce the processor logic utilization. FPGA offers a high level of parallelism which is exploited by the processor to implement the parallel process of edge detection in order to increase the processor throughput and enable the processor to meet real-time performance constraints. To achieve real-time performance, the proposed processor consists of several Sobel instances that are able to produce massive output pixels in parallel. This parallelism enables data reuse within the processor block which reduces the number of calculations while increasing the processor throughput. Moreover, the processor gains performance with a factor equal to the number of instances contained in the processor block. By the application of the optimization techniques, the proposed Sobel processor is able to meet real-time performance constraints due to its high throughput even with a considerably low clock frequency. In addition, the logic utilization of the proposed processor is low compared to other Sobel processors when implemented on ALTERA Cyclone II DE2-70 board

Item Type:Article
Academic Subject One:Academic Department - Electrical And Electronics - Pervasisve Systems - Digital Electronics - Microprocessor
Departments / MOR / COE:Centre of Excellence > Center for Intelligent Signal and Imaging Research
ID Code:11946
Deposited By: Dr Fawnizu Azmadi Hussin
Deposited On:07 Oct 2016 01:42
Last Modified:07 Oct 2016 01:42

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