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Resistive Open Faults Detectability Analysis and Implications for Testing Low Power Nanometric ICs

Mohammadat, Mohamed Tag Elsir and Zain Ali , Noohul Basheer and Hussin, Fawnizu Azmadi and Zwolinski, Mark (2015) Resistive Open Faults Detectability Analysis and Implications for Testing Low Power Nanometric ICs. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 23 (3). pp. 580-583. ISSN 1063-8210

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Abstract

Resistive open faults (ROFs) represent common manufacturing defects in IC interconnects and result in delay faults that cause timing failures and reliability risks. The nonmonotonic dependence of ROF-induced delay faults on the supply voltage (VDD) poses a concern as to whether single-VDD testing will suffice for low power nanometric designs. Our analysis shows multi-VDD tests could be required, depending on the test speed. This knowledge can be exploited in small delay fault testing to reduce the chances of test escapes while minimizing cost.

Item Type:Article
Academic Subject One:Academic Department - Electrical And Electronics - Pervasisve Systems - Digital Electronics - VLSI Design
Departments / MOR / COE:Centre of Excellence > Center for Intelligent Signal and Imaging Research
ID Code:11942
Deposited By: Dr Fawnizu Azmadi Hussin
Deposited On:07 Oct 2016 01:42
Last Modified:19 Jan 2017 08:20

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