Review of Single Cycle Shifter for Structured LDPC Encoder

Shifter has been used in encoder of structured low density parity check (LDPC) codes due
to the nature of its structure. Single clock cycle time of shifter is selected for doing matrix-vector
multiplication of LDPC encoding to minimize encoding latency. Among the shifters which complete
the multiplication within one clock cycle, this paper suggests the cyclic shifter for structured LDPC
encoder. It is shown that the implementation of the typical cyclic shifter has less logic gates and less
bit controller than the other shifter.